List of Figures

| Table of Contents | List of Figures | List of Examples | List of Tables |

Figure 1-1. CPU Access to Memory

Figure 1-2. CPU Access to Device Registers (Programmed I/O)

Figure 1-3. Device Access to Memory

Figure 1-4. Device Access Through a Bus Adapter

Figure 1-5. The 32-Bit Address Space

Figure 1-6. MIPS 32-Bit Virtual Address Format

Figure 1-7. Main Parts of the MIPS R10000 Microprocessor 64-Bit Address Space

Figure 1-8. Selecting the MIPS 64-Bit Address Space Segments

Figure 1-9. MIPS 64-Bit Virtual Address Format

Figure 1-10. Address Decoding for Physical Memory Access

Figure 1-11. SGI Origin 2000 Physical Address Decoding

Figure 1-12. SGI Origin 2000 Fetch-and-Op Address Decoding

Figure 2-1. Part of a Typical Hwgraph

Figure 3-1. Overview of Device Open

Figure 3-2. Overview of Device Control

Figure 3-3. Overview of Programmed Kernel I/O

Figure 3-4. Overview of Memory Mapping

Figure 3-5. Overview of DMA I/O

Figure 5-1. Bit Assignments in SCSI Device Minor Numbers

Figure 8-1. Address/Length List Concepts

Figure 12-1. Relationship of VME Bus to System Bus

Figure 12-2. VME Bus Enclosure and Cable to an Origin 2000 Deskside

Figure 12-3. VME Bus Connection to System Bus

Figure 14-1. Relationship of VME Bus to System Bus

Figure 14-2. VMECC, the VMEbus Adapter

Figure 14-3. I/O Address to System Address Mapping

Figure 14-4. VMECC Contribution to VME Handshake Cycle Time

Figure 16-1. SCSI Vertexes and Data Structures

Figure 17-1. Overview of Network Architecture

Figure 18-1. High-Level Overview of EISA Bus in Indigo2 

Figure 18-2. Encoding of the EISA Manufacturer ID

Figure 19-1. The SysAD Bus in Relation to GIO

Figure 20-1. PCI Bus In Relation to System Bus