Table 2-2 shows how the various connectors correspond to IRIX (operating system) special device files.

For more information about serial devices, see serial(7). For information about the parallel port, see plp(7). For more information about SCSI devices and device names, see dks(7M) (for disks) and tps(7M) (for tape drives).

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Note: You cannot install your boot (system) disk on SCSI controllers 4 and 5. You can attach a boot (system) disk only to controller 0.

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The module consists of the CPU (an R4600, R4400, or R5000) with built-in floating-point unit (FPU) and primary cache, a 512 KB (R5000) or 1 MB (R4400) secondary cache, and an oscillator to set the processor speed. The CPU module is connected to the memory subsystem by a 64-bit (plus parity) multiplexed address and data CPU Bus.

The CPU module is replaceable separate from the system board. See Table 2-1 for a complete description of the CPU features.

This system board contains:

The section “System Buses and I/O Channels,” describes the architecture of the system.

The IOPLUS board provides

The IOPLUS connects to the two GIO slots on the system board, and mounts on standoffs.

The Challenge S server contains several custom ASICs to aid communication between the system and the buses:

The R4000^® family of CPUs uses superpipelining to achieve fast internal speeds. In normal pipelining, the CPU breaks each instruction into separate one-cycle steps (usually fetch, read, execute, memory, and write back), then executes instructions at one-cycle intervals. Pipelining allows instructions to overlap, providing close to one instruction per cycle instead of one instruction every five cycles.

At the fast R4400 and R4600 CPU clock rates, some instruction steps such as cache reads and writes can't execute in a single pipelined cycle. Superpipelining executes each of these critically slow steps in a single cycle to provide higher throughput. To do so, it first breaks instruction steps into substeps. The substeps are then pipelined in a process separate from standard pipelining, which executes the full step in a single cycle. R4000 superpipelining is optimized so that it requires little control logic and instruction structure, unlike SuperScalar implementations.

The R4000 family of CPUs supports both the MIPS I and MIPS III instruction sets. Data pathways in MIPS III are 64 bits wide, enabling the system to load and store full floating point double words in a single machine cycle. The MIPS III instruction set also contains synchronization and advanced cache control primitives.

The R5000 CPU implements the MIPS IV instruction set. This instruction set provides four floating point multiply-add/subtract instructions which allow two separate floating point computations to be performed with one instruction. The R5000 processor also boosts its floating-point performance by reducing the repeat rate of many instructions from 2 cycles to 1. This allows those instructions critical to 3-D applications to be issued on every cycle, as opposed to every other cycle.

Separate integer and floating point arithmetic logic units (ALU's) allow a floating point ALU instruction to be issued simultaneously with any other instruction type. Whenever a floating point ALU instruction is fetched with any non-floating point ALU instruction, both instructions can be issued in the same cycle. Integer instructions do not have to wait for long-latency floating point operations to finish before being fetched, and vice versa. Load/store operations may also be issued simultaneously with floating point ALU instructions to reduce load latencies and bandwidth.

Like the R4400, the R5000 contains large, 32 KB instruction and data caches. Each cache is 2-way set associative, which helps to increase the hit rate over a direct-mapped implementation, and has a 32-byte fixed line size. Cache lines may be classified as write-through or write-back on a per-page basis.

The CPU subsystem is connected to the memory subsystem by a 64-bit wide (plus parity) data and address CPU bus. This bus consists of the R4600, R4400, and R5000 bus and control signals from the memory subsystem. Both can transfer data at a peak rate of 400 MB per second to and from the memory subsystem.

The memory subsystem contains memory control, data bus routing, and 8 SIMM sockets for main memory. A 64-bit (plus parity) multiplex address and data GIO64 bus connects the memory subsystem to I/O and the GIO expansion subsystems.

The memory subsystem uses two types of custom chips, the MC1 ASIC and the DMUX1 ASIC, to give the CPU access to main memory and the GIO64 bus and to isolate the CPU bus from the GIO64 bus.

The MC1 ASIC, the memory controller (shown in Figure 2-8), is a custom Silicon Graphics chip connected to the CPU module by the CPU bus. It's also connected to the GIO64 bus (the I/O bus), and has address and control lines connected to main memory. It performs a number of functions:

The DMUX1 ASICs are a two-chip slice of a data crossbar between the CPU, main memory, and the GIO64 bus. The two DMUX1 chips are, together, a data path with control signals generated by the MC1. They isolate the CPU bus from the memory system and the GIO64 bus. They also contain synchronization FIFOs to perform flow control between the various subsystems and they interleave main memory to increase peak memory bandwidth.

Main Memory

Main memory is controlled by the MC1 and DMUX1 ASICs. Memory consists of 72-pin, 36-bit wide DRAM SIMMs (which must have 80 ns RAS access time and fast page-mode capability). Challenge S supports the following SIMM types:

• 4 MB

• 8 MB

• 16 MB

• 32 MB

SIMMS are arranged in slots and banks, as shown in Figure 2-9.

Figure 2-9. SIMM Bank and Slot Arrangement

DMUX1 chips interleave the SIMMs to create a 72-bit wide, two-way interleaved memory system. See Figure 2-10.

Figure 2-10. Memory Block on the Challenge S System Board

Main memory can be configured for between 16 MB and 256 MB. The system board has 8 SIMM sockets, arranged in two banks of four. Each bank must use SIMMs of the same size, but SIMM sizes can differ between banks.

The GIO64 bus, the main system bus, provides a 64-bit wide (plus parity) data path and is designed for very high speed data transfer. It connects the Challenge S main systems: the CPU, memory, I/O, and GIO expansion slots. The GIO64 is a synchronous, multiplexed address/data burst mode bus that runs at 33 MHz and is clocked independently of the CPU. The GIO64 bus can transfer data between main memory and any device on the bus at up to 267 MB per second.

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Note: The GIO interface is a published specification available to developers.

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The HPC3 ASIC (high performance peripheral controller) is the heart of the I/O subsystem. It is a custom Silicon Graphics chip that collects data from relatively slow peripherals, buffers it in FIFOs, then transfers it into main memory using high speed DMA transfers over the GIO64 bus. It also transfers data from main memory to peripheral devices in the same manner.

The HPC3 has direct interfaces to the GIO64 bus, to a SCSI-2 port, to an Ethernet port, and to the 16-bit P-Bus (peripheral bus). The SCSI-2 and Ethernet ports are connected directly for increased bandwidth. The P-Bus is a 20-bit address, 16-bit data bus used by the HPC3 for additional peripheral support. It connects the boot PROM, a real-time clock, the ISDN interface, and the IOC1 ASIC. The IOC1 integrates an interrupt handler, two general purpose serial ports, and a parallel port. There is a 384-byte memory buffer that is shared by all of the P-Bus devices to buffer DMA transfers to and from memory.

The IOPLUS I/O expansion subsystem includes its own HPC3 ASIC connected directly to the GIO64 bus. This additional HPCS supports the additional Ethernet controller and the two Fast and Wide SCSI-2 controllers provided by the optional subsystem.

SCSI-2 Ports

The standard 10 MB per second, Fast SCSI-2 interface consists of one controller (controller 0) shared between internal and external devices. The controller supports two internal SCSI devices, and up to five external SCSI devices (provided the external cable length does not exceed two meters), through a high-density, single-ended SCSI port on the rear of the system unit.

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Note: Because of cable-length restrictions, you may be limited to three external devices on SCSI controller 0. For example, if you use a one-meter cable to attach the first device, and half-meter cables for each additional device, this totals two meters of cable–the maximum cable length.

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The Fast SCSI-2 controller is supported by a SCSI controller connected directly to the HPC3 ASIC. The HPC3 uses a FIFO buffer to enable burst use of the GIO64 bus.

The IOPLUS I/O expansion subsystem provides two additional Fast, Wide, and differential SCSI-2 controllers (controllers 4 and 5) providing 20 MB of maximum bandwidth per controller (40 MB total). These controllers support a maximum of 18 meters of cable length. Be aware that these controllers are not active until the system has already started booting.

Silicon Graphics defines bus speeds for its SCSI controllers in megatransfers per second. Megatransfers are the number of million operations per bus cycle. An operation is either 8 or 16 bits in size. Megatransfers are based on a bus's burst data rate. Total data transfer rates depend on the bus bandwidth.

ISDN Port

Challenge S supports a single ISDN basic rate interface integrated onto the system board. Access to the ISDN is provided at the “S” access point. The design provides a single hardware implementation that is certifiable throughout the world.

With IRIX 5.3, the subsystem isdn_eoe must be installed in order for the ISDN interface to operate. ISDN for the Challenge S server works with the following switch protocols in the United States:

• DMS100

• 5ESS

• National ISDN1

ISDN on the Challenge S server has been approved for the following switch protocols in the following countries:

• 1TR6 in Germany

• Euro-ISDN in Germany, Sweden, and Finland

• NTT in Japan

Countries other than those listed above may require testing and approval before ISDN can be used with the Challenge S server in that country. Contact your local service provider or Silicon Graphics for more information.

The ISDN Basic Rate Interface on the Challenge S server supports the Point-to-Point Protocol (PPP). PPP enables TCP/IP networking across ISDN B-channels, providing the full 64 kilobits (Kb) per second bandwidth of each B-channel. Both B channels can be combined using a round-robin packet-sending scheme to maximize throughput. This is sometimes called inverse multiplexing, and is similar to bonding.

The Application Software Interface (ASI) being developed by the National ISDN User's Forum is expected to become a standard in the USA. For information on programing with ASI, see the isdn_eoe Release Notes (available on-line using the relnotes command).

ISDN features include

• a single “S” RJ45 access connector

• hardware HDLC framing on both B-channels for data communications and networking applications

• three DMA channels (one channel to transmit and one for each receive direction on each B-channel)

• separate 64-byte transmit and receive FIFOs on each B-channel and on the D-channel

A block diagram of the Challenge S ISDN architecture is shown in Figure 2-11.

Figure 2-11. ISDN Interface Architecture

The interface is based on the S interface chip and the HDLC controller chip. The S interface chip provides the interface to the four-wire S interface, HDLC formatting on the D-channel, two FIFOs for the D-channel transmit and receive data, and host access to the D-channel data. The HDLC controller chip provides the DMA interface to the B-channels, HDLC formatting on the B-channels, and four FIFOs for the B-channel transmit and receive data. The isolation transformers provide the coupling and high voltage isolation between the S interface and the Challenge S system.

The S interface chip and the HDLC controller chip are both connected to the P-Bus in the Challenge S system. Both chips contain registers that may be accessed by the host CPU. The HDLC controller chip is connected to three DMA channels that are contained in the HPC3 ASIC.

The two GIO32-bis expansion slots, connected directly to the GIO64 bus, provide direct access to the system for Silicon Graphics and third party plug-in boards for such applications as high-speed networking, image compression, video deck control, and additional I/O.

GIO32-bis is a cross between GIO32 and GIO64. It can be considered a 32-bit version of the non-pipelined GIO64 or a GIO32 with pipelined control signals.

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Note: Only GIO slot 0 has DMA available for option boards. (See Figure 2-7.) If a GIO option board uses DMA, it must be installed in slot 0. The only exceptions to this rule are the Silicon Graphics GIO32 SCSI and Ethernet E++ boards.

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Table 2-3 lists the GIO slot dependencies.