List of Figures

| Table of Contents | List of Figures | List of Tables |

Figure 1. Organization of this Manual

Figure 1-1. Origin System Datapaths

Figure 1-2. Origin Family Components: System and Modules

Figure 1-3. User-Addressable Virtual Address Space

Figure 1-4. Virtual Address Bit Mappings

Figure 1-5. Physical Address Space

Figure 1-6. Cache Lines and Memory Pages

Figure 1-7. Physical Address Space Fields

Figure 1-8. M Mode Physical Address Fields

Figure 1-9. Conversion of NASIDs to Hub Internal Addresses

Figure 2-1. M Mode Physical Address Space

Figure 2-2. Cac Space Addressing

Figure 2-3. BDDir Space Map

Figure 2-4. HSpec Address Used for Accessing a Directory Entry in M Mode

Figure 2-5. HSpec Address for Accessing the M Mode Protection and Page Reference Count

Figure 2-6. HSpec Address Used for Accessing the Backdoor ECC (BDECC)

Figure 2-7. Read/Write Organization of the Flash PROM

Figure 2-8. Processor 0/1 Address Mapping in Ualias

Figure 3-1. I/O Map (Per Node) as it Appears to the Processor

Figure 3-2. Hub Local Register Space

Figure 3-3. Hub Chip Interfaces

Figure 3-4. Accessing the Hub Local Registers in LWin Space

Figure 3-5. BWin Space Access in M Mode

Figure 4-1. XIO Memory View Address Map

Figure 4-2. Memory View Access in M Mode

Figure 4-3. M Mode Addressing in an XIO IO View

Figure 4-4. I/O View Access in M Mode

Figure 4-5. XIO IO View Map